IPMI on Intel architecture (IA)

IPMI works very well with the Intel architecture. To take full advantage of IPMI, Intel designs specific features into processors and chipsets in order to meet demanding mangeability requirements from a winde range of costumers. Of course what is implemented in the Pentium/Xeon family processor won't work on other architectures. The Intel processors can emit some signals such as an example:

• PROCHOT# The maximum safe operating temperature reached
• THERMTRIP# Processor junction temperature critical
• VID For selection of power supply voltages
• IERR# Internal procesor error
• FERR# Floating point error from numeric coprocessor
• AERR# Address error
• BERR# Bus error

Just as another example, processors assert PROCHOT# when activating a thermal control circuit that can autmatically throttle processor clock speed. When the junction temperature exceeds a critical threshold a processor asserts THERMTRIP#. Upon a THERMTRIP# trigger, Intel processors attempt to stop internal clocks and halt the program execution to reduce interanl temperature and avoid processor damage. On some systems, the firmware present in the BMC , can increase fan speeds or , can raise system interrupts for the ACPI functions. The firmware can logs all the alarms in the IPMI defined Systen Event Log, SEL. If there are too many thermal events within a configurable time frame, the firmware generates an IPMI defined platform event trap (PET). This is an SNMP trap. The five VID signals on the processor may be used to control the voltage of the voltage regulator. IERR# indicates a catastrophic error. We can store all the IERRs, for example, in the SEL, and monitor them in the case of many multiprocessor machine. AERR# is a Bus parity error. BERR# indicates a bus protocol violation. Pay attention to this: analyzing the frequencies of the BERR# may be an index of a probable fault!!! We can use it to predict fauilures or to train some MLPs.In the XEON processors there is a ROM called Processor Information ROM, PIROM. In this PIROM, the XEON can write data to pass directly to the BMC. The INTRUDER# determines (when assert) if a chassis has been opened. SERR# means for system errors. On the IA chipsets the BMC can have ceratins functions: WAKE#, that wake up the systems, Unconditional PowerDown, hard reset without cycling the UPS, and so on. The OSA, firmware architecture supports something like ``modules'' The main communication channels of OSA firmware are $I^2C$, IPMB, ICMB, RS232, RS485, Emergency Management Protocol (EMP) RMCP, IP, TCP, UDP via integrated NIC.